ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 47. Input signals are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 47. S/PDIF Transmitter Input Data Timing
88-Lead LFCSP Package All Other Packages
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSISFS1
Frame Sync Setup Before Serial Clock Rising Edge 4.5
3
ns
tSIHFS1
Frame Sync Hold After Serial Clock Rising Edge
3
3
ns
tSISD1
Data Setup Before Serial Clock Rising Edge
4.5
3
ns
tSIHD1
Data Hold After Serial Clock Rising Edge
3
3
ns
tSITXCLKW
Transmit Clock Width
9
9
ns
tSITXCLK
Transmit Clock Period
20
20
ns
tSISCLKW
Clock Width
36
36
ns
tSISCLK
Clock Period
80
80
ns
1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input
can be either CLKIN or any of the DAI pins.
DAI_P20–1
(TxCLK)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
tSITXCLKW
SAMPLE EDGE
tSITXCLK
tSISCLKW
tSISCLK
tSISFS
tSISD
tSIHFS
tSIHD
Figure 34. S/PDIF Transmitter Input Timing
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter requires an oversampling clock input.
This high frequency clock (TxCLK) input is divided down to
generate the internal biphase clock.
Table 48. Oversampling Clock (TxCLK) Switching Characteristics
Parameter
Frequency for TxCLK = 384 × Frame Sync
Frequency for TxCLK = 256 × Frame Sync
Frame Rate (FS)
Max
Oversampling Ratio × Frame Sync ≤ 1/tSITXCLK
49.2
192.0
Unit
MHz
MHz
kHz
Rev. C | Page 54 of 76 | July 2013
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