ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
MLBSIG/
MLBDAT
(Rx, Input)
MLBCLK
MLBSIG/
MLBDAT
(Tx, Output)
VALID
tDSMCF
tMCKH
tMCKR
tMCDRV
tMCKF
tMLBCLK
tMCFDZ
tMDZH
VALID
tDHMCF
tMCKL
Figure 38. MLB Timing (3-Pin Interface)
Table 53. MLB Interface, 5-Pin Specifications
Parameter
Min
Typ
Max
Unit
5-Pin Characteristics
tMLBCLK
MLB Clock Period
512 FS
256 FS
40
ns
81
ns
tMCKL
MLBCLK Low Time
512 FS
15
ns
256 FS
30
ns
tMCKH
MLBCLK High Time
512 FS
15
ns
256 FS
30
ns
tMCKR
MLBCLK Rise Time (VIL to VIH)
tMCKF
MLBCLK Fall Time (VIH to VIL)
tMPWV1
MLBCLK Pulse Width Variation
tDSMCF2
DAT/SIG Input Setup Time
3
tDHMCF
DAT/SIG Input Hold Time
5
tMCDRV
tMCRDL3
DS/DO Output Data Delay From MLBCLK Rising Edge
DO/SO Low From MLBCLK High
512 FS
256 FS
6
ns
6
ns
2
ns p-p
ns
ns
8
ns
10
ns
20
ns
Cmlb
DS/DO Pin Load
40
pf
1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (p-p).
2 Gate delays due to OR’ing logic on the pins must be accounted for.
3 When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset,
external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven.
Rev. C | Page 59 of 76 | July 2013
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