ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
SPI Interface—Slave
Table 51. SPI Interface Protocol—Slave Switching and Timing Specifications
88-Lead LFCSP Package All Other Packages
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSPICLKS
Serial Clock Cycle
4 × tPCLK – 2
4 × tPCLK – 2
ns
tSPICHS
Serial Clock High Period
2 × tPCLK – 2
2 × tPCLK – 2
ns
tSPICLS
Serial Clock Low Period
2 × tPCLK – 2
2 × tPCLK – 2
ns
tSDSCO
SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1 2 × tPCLK
2 × tPCLK
ns
tHDS
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
2 × tPCLK
2 × tPCLK
ns
tSSPIDS
Data Input Valid to SPICLK Edge (Data Input Setup Time)
2
2
ns
tHSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid
2
2
ns
tSDPPW
SPIDS Deassertion Pulse Width (CPHASE = 0)
2 × tPCLK
2 × tPCLK
ns
Switching Characteristics
tDSOE
tDSOE1
tDSDHI
tDSDHI1
tDDSPIDS
tHDSPIDS
tDSOV
SPIDS Assertion to Data Out Active
SPIDS Assertion to Data Out Active (SPI2)
SPIDS Deassertion to Data High Impedance
SPIDS Deassertion to Data High Impedance (SPI2)
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE = 0)
0
0
0
0
2 × tPCLK
13
13
2 × tPCLK
2 × tPCLK
13
5 × tPCLK
0
0
0
0
2 × tPCLK
10.25 ns
10.25 ns
13.25 ns
13.25 ns
11.5
ns
ns
5 × tPCLK ns
1 The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral
Interface Port (SPI)” chapter.
SPIDS
(INPUT)
SPICLK
(CP = 0,
CP = 1)
(INPUT)
tSDSCO
tDSOE
MISO
(OUTPUT)
CPHASE = 1
MOSI
(INPUT)
tSPICHS
tDDSPIDS
MISO
(OUTPUT)
tDSOV
CPHASE = 0
MOSI
(INPUT)
tSPICLS
tSPICLKS
tHDS
tSDPPW
tDDSPIDS
tSSPIDS tHSPIDS
tDSDHI
tHDSPIDS
tSSPIDS
tHDSPIDS
tHSPIDS
tDSDHI
Figure 37. SPI Slave Timing
Rev. C | Page 57 of 76 | July 2013
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