AT91SAM9263B-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91SAM9263B-CU' PDF : 52 Pages View PDF
REMAP allows the user to layout the internal SRAM bank to 0x0. This is done by software once the system has booted.
Refer to the section “AT91SAM9263 Bus Matrix” in the product datasheet for more details.
When REMAP = 0, BMS allows the user to layout at address 0x0 either the ROM or an external memory. This is done via
hardware at reset.
Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the
complete memory map presented in Figure 8-1 on page 20.
The AT91SAM9263 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal
memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface.
8.1.2.1 BMS = 1, Boot on Embedded ROM
The system boots on Boot Program.
z Boot at slow clock
z Auto baudrate detection
z Downloads and runs an application from external storage media into internal SRAM
z Downloaded code size depends on embedded SRAM size
z Automatic detection of valid application
z Bootloader on a non-volatile memory
z SD Card
z NAND Flash
z SPI DataFlash® and Serial Flash connected on NPCS0 of the SPI0
z Interface with SAM-BA® Graphic User Interface to enable code loading via:
z Serial communication on a DBGU
z USB Bulk Device Port
8.1.2.2 BMS = 0, Boot on External Memory
z Boot at slow clock
z Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write
controlled by Chip Select, allows boot on 16-bit non-volatile memory.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI0 CS0 (BMS=0) the user must:
1. Program the PMC (main oscillator enable or bypass mode).
2. Program and Start the PLL.
3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock.
4. Switch the main clock to the new value.
8.2 External Memories
The external memories are accessed through the External Bus Interfaces 0 and 1. Each Chip Select line has a 256
Mbyte memory area assigned.
Refer to Figure 8-1 on page 20.
8.2.1
External Bus Interfaces
The AT91SAM9263 features two External Bus Interfaces to offer more bandwidth to the system and to prevent
bottlenecks while accessing external memories.
SAM9263 [Summary] 23
6249IS–ATARM–28-Jan-13
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