AT91SAM9263B-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91SAM9263B-CU' PDF : 52 Pages View PDF
9.2 Reset Controller
z Based on two Power-on-Reset cells
z One on VDDBU and one on VDDCORE
z Status of the last reset
z Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or
watchdog reset
z Controls the internal resets and the NRST pin output
z Allows shaping a reset signal for the external devices
9.3 Shutdown Controller
z Shutdown and Wake-up logic
z Software programmable assertion of the SHDN pin (SHDN is push-pull)
z Deassertion programmable on a WKUP pin level change or on alarm
9.4 Clock Generator
z Embeds the low-power 32768 Hz Slow Clock Oscillator
z Provides the permanent Slow Clock SLCK to the system
z Embeds the Main Oscillator
z Oscillator bypass feature
z Supports 3 to 20 MHz crystals
z Embeds 2 PLLs
z Output 80 to 240 MHz clocks
z Integrates an input divider to increase output accuracy
z 1 MHz Minimum input frequency
Figure 9-2. Clock Generator Block Diagram
IN32
OUT32
IN
OUT
Clock Generator
Slow Clock
Oscillator
Slow Clock
SLC
Main
Oscillator
Main Clock
MAINC
PLLRCA
PLL and
Divider A
PLLA Clock
PLLAC
PLLRCB
PLL and
Divider B
PLLB Clock
PLLBC
Status Control
Power
Management
Controller
9.5 Power Management Controller
z Provides:
SAM9263 [Summary] 27
6249IS–ATARM–28-Jan-13
Share Link: 
