8.2.1.1 External Bus Interface 0
z Integrates three External Memory Controllers:
z Static Memory Controller
z SDRAM Controller
z ECC Controller
z Additional logic for NAND Flash and CompactFlash
z Optional Full 32-bit External Data Bus
z Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select)
z Up to 6 Chip Selects, Configurable Assignment:
z Static Memory Controller on NCS0
z SDRAM Controller or Static Memory Controller on NCS1
z Static Memory Controller on NCS2
z Static Memory Controller on NCS3, Optional NAND Flash support
z Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
z Optimized for Application Memory Space
8.2.1.2 External Bus Interface 1
z Integrates three External Memory Controllers:
z Static Memory Controller
z SDRAM Controller
z ECC Controller
z Additional logic for NAND Flash
z Optional Full 32-bit External Data Bus
z Up to 23-bit Address Bus (up to 8 Mbytes linear)
z Up to 3 Chip Selects, Configurable Assignment:
z Static Memory Controller on NCS0
z SDRAM Controller or Static Memory Controller on NCS1
z Static Memory Controller on NCS2, Optional NAND Flash support
z Allows supporting an external Frame Buffer for the embedded LCD Controller without impacting processor
performance.
8.2.2
Static Memory Controller
z 8-, 16- or 32-bit Data Bus
z Multiple Access Modes supported
z Byte Write or Byte Select Lines
z Asynchronous read in Page Mode supported (4- up to 32-byte page size)
z Multiple device adaptability
z Compliant with LCD Module
z Control signals programmable setup, pulse and hold time for each Memory Bank
z Multiple Wait State Management
z Programmable Wait State Generation
z External Wait Request
z Programmable Data Float Time
z Slow Clock mode supported
8.2.3 SDRAM Controller
z Supported devices
SAM9263 [Summary] 24
6249IS–ATARM–28-Jan-13