AT91SAM9263B-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91SAM9263B-CU' PDF : 52 Pages View PDF
z Standard and Low-power SDRAM (Mobile SDRAM)
z Numerous configurations supported
z 2K, 4K, 8K Row Address Memory Parts
z SDRAM with two or four Internal Banks
z SDRAM with 16- or 32-bit Data Path
z Programming facilities
z Word, half-word, byte access
z Automatic page break when Memory Boundary has been reached
z Multibank Ping-pong Access
z Timing parameters specified by software
z Automatic refresh operation, refresh rate is programmable
z Energy-saving capabilities
z Self-refresh, power down and deep power down modes supported
z Error detection
z Refresh Error Interrupt
z SDRAM Power-up Initialization by software
z CAS Latency of 1, 2 and 3 supported
z Auto Precharge Command not used
8.2.4
Error Corrected Code Controller
z Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select
z Single-bit error correction and two-bit random detection
z Automatic Hamming Code Calculation while writing
z ECC value available in a register
z Automatic Hamming Code Calculation while reading
z Error Report, including error flag, correctable error flag and word address being detected erroneous
z Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte pages
9. System Controller
The System Controller is a set of peripherals that allow handling of key elements of the system, such as power, resets,
clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds registers that are used to configure the Bus Matrix and a set of
registers for the chip configuration. The chip configuration registers can be used to configure:
z EBI0 and EBI1 chip select assignment and voltage range for external memories
z ARM Processor Tightly Coupled Memories
The System Controller peripherals are all mapped within the highest 16 Kbytes of address space, between addresses
0xFFFF C000 and 0xFFFF FFFF.
However, all the registers of the System Controller are mapped on the top of the address space. This allows all the
registers of the System Controller to be addressed from a single pointer by using the standard ARM instruction set, as
the Load/Store instructions have an indexing mode of ± 4 Kbytes.
Figure 9-1 on page 26 shows the System Controller block diagram.
Figure 8-1 on page 20 shows the mapping of the User Interfaces of the System Controller peripherals.
SAM9263 [Summary] 25
6249IS–ATARM–28-Jan-13
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