CL-PS6700-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS6700-VC-A' PDF : 48 Pages View PDF
CL-PS6700
Low-Power PC Card Controller
4.3 Power Management Registers
4.3.1 Power Management Register (0X0C002800)
Bit(s)
15:14
13
12
11:10
9
8
7
6
5
4
3
2
1
0
Description
Default R/W
Reserved
00 R/W
Disable Protection for PCM_BVD[1] Input During Card Power Off.The input pull-up is con-
0
R/W
trolled in the same way as other card inputs.
Input Pull-Up Enable. This bit applies to card inputs BVD[2], BVD[1], RDY, WAIT, WP. During
0
R/W
CardOut or Standby, the pull-up resistors are disconnected and inputs are protected regard-
less of the state of this bit. ‘Protected input’ (PI) means the input can float without causing
excessive current.
CardOut means that the Card Detect inputs are high (no card inserted) or that the card power
is off (Card Power Enable bit 5 is low and Monitor Card Power Enable bit 6 is high).
Card Detect. Weak internal pull-up resistor.
00 R/W
00 – Pull-up is off and Card Detect inputs are not protected. This assumes that there are
external pull-up resistors.
01 – Pull-up is off and Card Detect inputs are protected.
10 – Weak pull-up, except when in Standby mode.
11 – Weak pull-up always on. This allows Card Detect during Standby.
Standby Request During Card Access. This bit controls pending card accesses when enter-
0
R/W
ing Standby mode.
0 – Abort any card access when entering Standby mode.
1 – Complete pending card access, then halt.
Standby Disable. When this bit is set, the PSLEEP_L input is effectively disabled.
0
R/W
PDREQ_L Select. If this bit is set, the PDREQ_L pin is a GPIO pin.
0
R/W
Monitor Card Power Enable (Bit 5).
0
R/W
0 – Card power is assumed to be always on.
1 – Enable monitoring of power.
This bit has no effect on card power or the CL-PS6700 power modes such as Standby and
Idle.
Card Power Enable.
0
R/W
0 – Outputs state of bits [5:3] of Card Power Control register to the PCTL[2:0] pins.
1 – Outputs state of bits [2:0] of Card Power Control register to the PCTL[2:0] pins.
If card access is attempted with this bit clear, a RD_FAIL or WR_FAIL interrupt can be gener-
ated.
Auto Disable Card Access on Card Removal. If this bit is set, the Card Enable bit (bit 10 in
0
R/W
the Card Interface Configuration register) is cleared when the card is removed.
Auto Power Down Card on Card Removal. If this bit is set, the Card Power Enable bit (bit 5)
0
R/W
is cleared when the card is removed.
Auto Power Down Card on Standby. If this bit is set, the Card Power Enable bit (bit 5) is
0
R/W
cleared when Standby mode is entered.
Idle. When this bit is set, it forces the CL-PS6700 into Low Power mode. Most internal clocks
0
R/W
are stopped with the exception of register access. Idle mode has no affect on I/O pads or card
power control.
Enable Auto Idle Mode. When this bit is set, some internal clocks are stopped whenever the
0
R/W
CL-PS6700 is idle.
24
REGISTERS
CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED
PRELIMINARY DATA BOOK v1.0
November 1997
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