CL-PS6700-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS6700-VC-A' PDF : 48 Pages View PDF
CL-PS6700
Low-Power PC Card Controller
4.5.2 Card Interface Timing Register 0A (0X0C003000)
Bit(s)
15:14
13:8
7:6
5:0
Description
Default R/W
Prescaler Field for Watchdog Timer.
00 – Divide by 1
01 – Divide by 16
10 – Divide by 256
11 – Divide by 8192
00 R/W
Count Field for Watchdog Timer. Settings of 00 to 3Fh correspond to values between 1 and 1Fh R/W
64 times the prescale value. The period starts at the end of the command width period and
continues as long as PCM_WAIT_L is low. If terminal count is reached, an interrupt can be
generated.
Prescaler Field for Command Strobe Width.
00 – Divide by 1
01 – Divide by 16
10 – Divide by 256
11 – Divide by 8192
00 R/W
Count Field for Command Strobe Width. This field has values between 1 and 64. The com- 00h R/W
mand width equals:
tCMD = tPCLK × ([Prescale × Count] + 2)
4.5.3 Card Interface Timing Register 0B (0X0C003400)
Bit(s)
15:14
13:8
7:6
5:0
Description
Default R/W
Prescaler Field for Address and Data Hold Time.
00 – Divide by 1
01 – Divide by 16
10 – Divide by 256
11 – Divide by 8192
00 R/W
Count Field for Hold Period. Settings of 00 to 3Fh correspond to 1 to 64 times the prescale 00h R/W
value. The period starts at the end of the command strobe. The hold time equals:
tHold = tPCLK × ([Prescale × Count] + 1) + constant
Prescaler Field for Address and Data Setup Time.
00 – Divide by 1
01 – Divide by 16
10 – Divide by 256
11 – Divide by 8192
0
R/W
Count Field for Address and Data Setup Time. Settings of 00 to 3Fh correspond to 1 to 64
0
R/W
times the prescale value. The period starts at valid address and ends when the command
strobe is active. The setup time equals:
tsetup = tPCLK × ([Prescale × Count] + 1) − constant
November 1997
CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED
PRELIMINARY DATA BOOK v1.0
29
REGISTERS
Share Link: 
