CL-PS6700-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS6700-VC-A' PDF : 48 Pages View PDF
CL-PS6700
Low-Power PC Card Controller
4.4 System Interface Registers
4.4.1 System Interface Configuration Register (0X0C002000)
Bit(s)
15:10
9
8
7
6
5
4
3
2
1:0
Description
Default R/W
Reserved
–
–
Enable Active Pull-up on Open-Drain Interrupt Outputs PIRQ_L[1:0]. During Standby, 0
R/W
active pull-up is disabled.
Enable Assembly and Disassembly. If this bit is set, assembly and disassembly of card 1
R/W
accesses by CPU or DMA is allowed. When this bit is cleared, the card transaction size is lim-
ited to the width of the card defined by the Card Interface Configuration register bit 7.
Enable Handshake Using Card Ready Signal.When this bit is set, a low-level on PCM_RDY 1
R/W
prevents access to the card. When this bit is cleared, RDY is ignored, but can still generate
interrupts.
Report Read Failure. When this bit is set, a read failure generates an RD_FAIL interrupt.
1
R/W
Read failure can occur due to a time-out condition. Normally, this bit should be cleared so the
CL-PS7111 reports read failures.
Endian Conversion Enable.
0 – Disable byte swapping
1
R/W
1 – Enable byte swapping
PC Cards are defined as little–endian, while the ARM CPU inside the CL-PS7111 can be
big–endian or little–endian.
Transaction Queue Enable. When this bit is set, it enables queuing one or more CL-PS7111 1
R/W
write operations. If this bit is cleared, then PRDY goes low after a write until the write is com-
plete.
Transaction Queue Threshold Control.
0 – FIFO THLD interrupt when two entries are free in queue.
1 – FIFO THLD interrupt when four entries are free in queue.
1
R/W
Transaction Queue Flush. Discard data in queue.
0
R/W
Reserved
00 R/W
26
REGISTERS
CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED
PRELIMINARY DATA BOOK v1.0
November 1997
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