CL-PS6700
Low-Power PC Card Controller
4.3.2 Card Power Control Register (0X0C002C00)
Bit(s) Description
Default R/W
15:14
VS[2:1] Direction.
0 – Input
1 – Output
Input pull–up resistors are weak. During Standby mode the pull–up resistors are disabled.
00 R/W
13:12 VS[2:1] Output Value.
00 R/W
11
GPIO Direction. See Note.
0 – Input
1 – Output
0
R/W
10
GPIO Output Value When Card Power Enable Bit is Low. See Note.
0
R/W
9
GPIO Output Value When Card Power Enable Bit is High. See Note.
0
R/W
8:6
PCTL[2:0] Direction.
0 – Input
1 – Output
00 R/W
5:3
PCTL[2:0] Output Value When Card Power Enable Bit is Low. PCTL[0] is a tristate output 000 R/W
only. PCTL[2:1] are bidirectional. The PCTL[2:1] input value is at the Interrupt Pins register
and can generate an interrupt while PCTL[0] cannot generate an interrupt.
2:0
PCTL[2:0] Output Value When Card Power Enable Bit is High.
000 R/W
NOTE: If Power Management register bit 7 is cleared, then this bit is a don’t care.
November 1997
CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED
PRELIMINARY DATA BOOK v1.0
25
REGISTERS