External Memory Expansion Port (Port A)
Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 (continued)
20 MHz4
30 MHz4
No.
Characteristics
Symbol
Expression
Unit
Min Max Min Max
134 CAS deassertion to data not valid
tOFF
(read hold time)
0.0
—
0.0
—
ns
135 Last CAS assertion to RAS
deassertion
tRSH
0.75 × TC − 4.0 33.5
—
21.0
—
ns
136 Previous CAS deassertion to RAS
deassertion
tRHCP
2 × TC − 4.0
96.0 — 62.7 —
ns
137 CAS assertion pulse width
138 Last CAS deassertion to RAS
deassertion5
BRW[1:0] = 00
tCAS
0.75 × TC − 4.0 33.5
—
21.0
—
ns
tCRP
1.75 × TC − 6.0 81.5
—
52.3
—
ns
• BRW[1:0] = 01
• BRW[1:0] = 10
• BRW[1:0] = 11
139 CAS deassertion pulse width
140 Column address valid to CAS
assertion
3.25 × TC − 6.0 156.5
102.2 —
ns
4.25 × TC − 6.0 206.5
135.5 —
ns
6.25 × TC – 6.0 306.5 — 202.1 —
ns
tCP
0.5 × TC − 4.0
21.0
—
12.7
—
ns
tASC
0.5 × TC − 4.0
21.0
—
12.7
—
ns
141 CAS assertion to column address not
tCAH
0.75 × TC − 4.0 33.5
—
21.0
—
ns
valid
142 Last column address valid to RAS
deassertion
tRAL
2 × TC − 4.0
96.0 — 62.7 —
ns
143 WR deassertion to CAS assertion
tRCS
0.75 × TC − 3.8 33.7
—
21.2
—
ns
144 CAS deassertion to WR assertion
tRCH
0.25 × TC − 3.7
8.8
—
4.6
—
ns
145 CAS assertion to WR deassertion
tWCH
0.5 × TC − 4.2
20.8
—
12.5
—
ns
146 WR assertion pulse width
tWP
1.5 × TC − 4.5
70.5
—
45.5
—
ns
147 Last WR assertion to RAS deassertion tRWL
1.75 × TC − 4.3 83.2
—
54.0
—
ns
148 WR assertion to CAS deassertion
tCWL
1.75 × TC − 4.3 83.2
—
54.0
—
ns
149 Data valid to CAS assertion (Write)
tDS
0.25 × TC − 4.0
8.5
—
4.3
—
ns
150 CAS assertion to data not valid (write)
tDH
0.75 × TC − 4.0 33.5
—
21.0
—
ns
151 WR assertion to CAS assertion
tWCS
TC − 4.3
45.7 — 29.0 —
ns
3-18
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor