DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'DSP56300FM' PDF : 148 Pages View PDF
External Memory Expansion Port (Port A)
Table 3-11 DRAM Page Mode Timings, Three Wait States1, 2, 3 (continued)
No.
Characteristics
Symbol
Expression4
Min Max Unit
152 Last RD assertion to RAS deassertion
tROH
3.5 × TC − 4.0 31.0 —
ns
153 RD assertion to data valid
154 RD deassertion to data not valid6
tGA
2.5 × TC − 7.0
— 18.0 ns
tGZ
0.0
—
ns
155 WR assertion to data active
0.75 × TC − 0.3 7.2
—
ns
156 WR deassertion to data high impedance
0.25 × TC
— 2.5 ns
1 The number of wait states for Page mode access is specified in the DCR.
2 The refresh period is specified in the DCR.
3 The asynchronous delays specified in the expressions are valid for DSP56364.
4 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 4 ¥ TC for
read-after-read or write-after-write sequences).
5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of
page-access.
6 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
Table 3-12 DRAM Page Mode Timings, Four Wait States1, 2, 3
No.
Characteristics
Symbol
Expression4
Min Max Unit
131 Page mode cycle time for two consecutive accesses of the
same direction.
Page mode cycle time for mixed (read and write) accesses.
132 CAS assertion to data valid (read)
133 Column address valid to data valid (read)
134 CAS deassertion to data not valid (read hold time)
135 Last CAS assertion to RAS deassertion
136 Previous CAS deassertion to RAS deassertion
137 CAS assertion pulse width
138 Last CAS deassertion to RAS assertion5
• BRW[1:0] = 00
• BRW[1:0] = 01
• BRW[1:0] = 10
• BRW[1:0] = 11
tPC
tCAC
tAA
tOFF
tRSH
tRHCP
tCAS
tCRP
2 × TC
50.0 — ns
1.25 × TC
45.0 — ns
2.75 × TC − 7.0
— 20.5 ns
3.75 × TC − 7.0
— 30.5 ns
0.0 — ns
3.5 × TC − 4.0
31.0 —
ns
6 × TC − 4.0
56.0 — ns
2.5 × TC − 4.0
21.0 —
ns
2.75 × TC − 6.0
—
—
ns
4.25 × TC − 6.0
—
—
ns
5.25 × TC − 6.0 46.5 —
ns
7.25 × TC − 6.0 66.5 —
ns
139 CAS deassertion pulse width
tCP
2 × TC − 4.0
16.0 — ns
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
3-23
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