DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'DSP56300FM' PDF : 148 Pages View PDF
External Memory Expansion Port (Port A)
Table 3-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 4
No.
Characteristics
Symbol
Expression5
66 MHz
80 MHz
Unit
Min Max Min Max
131 Page mode cycle time for two consecutive
tPC
accesses of the same direction
2 × TC
45.4 — 37.5 —
ns
Page mode cycle time for mixed (read and
write) accesses
1.25 × TC
41.1 — 34.4 —
ns
132 CAS assertion to data valid (read)
tCAC
133 Column address valid to data valid (read)
tAA
134 CAS deassertion to data not valid (read hold
tOFF
time)
1.5 × TC − 7.5
1.5 × TC − 6.5
2.5 × TC − 7.5
2.5 × TC − 6.5
— 15.2 —
—
ns
—
—
— 12.3 ns
— 30.4 —
—
ns
—
—
— 24.8 ns
0.0 — 0.0 —
ns
135 Last CAS assertion to RAS deassertion
136 Previous CAS deassertion to RAS
deassertion
tRSH
1.75 × TC − 4.0 22.5 — 17.9 —
ns
tRHCP
3.25 × TC − 4.0 45.2 — 36.6 —
ns
137 CAS assertion pulse width
138 Last CAS deassertion to RAS deassertion6
• BRW[1:0] = 00
• BRW[1:0] = 01
• BRW[1:0] = 10
• BRW[1:0] = 11
139 CAS deassertion pulse width
140 Column address valid to CAS assertion
141 CAS assertion to column address not valid
142 Last column address valid to RAS
deassertion
tCAS
tCRP
tCP
tASC
tCAH
tRAL
1.5 × TC − 4.0 18.7 — 14.8 —
ns
2.0 × TC − 6.0 24.4 — 19.0 —
ns
3.5 × TC − 6.0 47.2 — 37.8 —
ns
4.5 × TC − 6.0 62.4 — 50.3 —
ns
6.5 × TC − 6.0 92.8 — 75.3 —
ns
1.25 × TC − 4.0 14.9 — 11.6 —
ns
TC − 4.0
11.2 — 8.5 —
ns
1.75 × TC − 4.0 22.5 — 17.9 —
ns
3 × TC − 4.0
41.5 — 33.5 —
ns
143 WR deassertion to CAS assertion
144 CAS deassertion to WR assertion
145 CAS assertion to WR deassertion
146 WR assertion pulse width
tRCS
1.25 × TC − 3.8 15.1 — 11.8 —
ns
tRCH
0.5 × TC − 3.7
3.9
— 2.6 —
ns
tWCH
1.5 × TC − 4.2 18.5 — 14.6 —
ns
tWP
2.5 × TC − 4.5 33.5 — 26.8 —
ns
3-20
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor
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