DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'DSP56300FM' PDF : 148 Pages View PDF
External Memory Expansion Port (Port A)
Table 3-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 4 (continued)
No.
Characteristics
Symbol
Expression5
66 MHz
80 MHz
Unit
Min Max Min Max
147 Last WR assertion to RAS deassertion
tRWL
2.75 × TC − 4.3 33.4 — 26.8 —
ns
148 WR assertion to CAS deassertion
tCWL
2.5 × TC − 4.3 33.6 — 27.0 —
ns
149 Data valid to CAS assertion (write)
tDS
0.25 × TC − 3.7 0.1
—
—
—
ns
0.25 × TC − 3.0 —
— 0.1 —
ns
150 CAS assertion to data not valid (write)
tDH
1.75 × TC − 4.0 22.5 — 17.9 —
ns
151 WR assertion to CAS assertion
tWCS
TC − 4.3
10.9 — 8.2 —
ns
152 Last RD assertion to RAS deassertion
tROH
2.5 × TC − 4.0 33.9 — 27.3 —
ns
153 RD assertion to data valid
tGA
1.75 × TC − 7.5 — 19.0 —
—
ns
154 RD deassertion to data not valid7
1.75 × TC − 6.5 —
—
— 15.4 ns
tGZ
0.0 — 0.0 —
ns
155 WR assertion to data active
0.75 × TC − 0.3 11.1 —
9.1
—
ns
156 WR deassertion to data high impedance
0.25 × TC
— 3.8 — 3.1 ns
1 The number of wait states for Page mode access is specified in the DCR.
2 The refresh period is specified in the DCR.
3 The asynchronous delays specified in the expressions are valid for DSP56364.
4 There are no DRAMs fast enough to fit to two wait states Page mode @ 100 MHz (See Figure 3-11).
5 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 × TC for
read-after-read or write-after-write sequences).
6 BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
7 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
3-21
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