HT66F016 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F016' PDF : 116 Pages View PDF
HT66F016/HT66F017/HT68F016/HT68F017
HT66F016R/HT66F017R/HT68F016R/HT68F017R
However a compare match from Comparator A will also
automatically clear the TnON bit and thus generate the
Single Pulse output trailing edge. In this way the CCRA
value can be used to control the pulse width. A compare
match from Comparator A will also generate a TM inter-
rupt. The counter can only be reset back to zero when
the TnON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used.
The TnCCLR and TnDPX bits are not used in this Mode.
Capture Input Mode
To select this mode bits TnM1 and TnM0 in the TMnC1
register should be set to 01 respectively. This mode en-
ables external signals to capture and store the present
value of the internal counter and can therefore be used
for applications such as pulse width measurements.
The external signal is supplied on the TPn pin, whose
active edge can be either a rising edge, a falling edge or
both rising and falling edges; the active edge transition
type is selected using the TnIO1 and TnIO0 bits in the
TMnC1 register. The counter is started when the TnON
bit changes from low to high which is initiated using the
application program.
When the required edge transition appears on the TPn
pin, the present value in the counter will be latched into
the CCRA registers and a TM interrupt generated. Irre-
spective of what events occur on the TPn pin the coun-
ter will continue to free run until the TnON bit changes
from high to low. When a CCRP compare match occurs,
the counter will reset back to zero; in this way the CCRP
value can be used to control the maximum counter
value. When a CCRP compare match occurs from Com-
parator P, a TM interrupt will also be generated.
Counting the number of overflow interrupt signals from
the CCRP can be a useful method in measuring long
pulse widths. The TnIO1 and TnIO0 bits can select the
active trigger edge on the TPn pin to be a rising edge,
falling edge or both edge types. If the TnIO1 and TnIO0
bits are both set high, then no capture operation will take
place irrespective of what happens on the TPn pin, how-
ever it must be noted that the counter will continue to
run.
As the TPn pin is pin shared with other functions, care
must be taken if the TM is in the Input Capture Mode.
This is because if the pin is setup as an output, then any
transitions on this pin may cause an input capture oper-
ation to be executed. The TnCCLR and TnDPX bits are
not used in this Mode.
Counter Value
CCRP
YY
XX
TnON
Counter cleared
by CCRP
TnM [1:0] = 01
Counter Counter
Stop Reset
Resume
Pause
Time
TnPAU
TM capture
Active
edge
pin TPn_x
Active
edge
Active edge
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value
XX
YY XX
TnIO [1:0]
Value
00 Rising edge 01 Falling edge 10 Both edges
YY
11 Disable Capture
Capture Input Mode
Note:
1. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits
2. A TM Capture input pin active edge transfers the counter value to CCRA
3. The TnCCLR bit is not used
4. No output function -- TnOC and TnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal
to zero.
Rev. 1.40
72
November 22, 2016
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