HT66F016/HT66F017/HT68F016/HT68F017
HT66F016R/HT66F017R/HT68F016R/HT68F017R
· ADCR0 Register
Bit
7
6
5
4
3
Name START EOCB ADOFF ADRFS
¾
R/W
R/W
R
R/W
R/W
¾
POR
0
1
1
0
¾
2
1
0
¾
ACS1
ACS0
¾
R/W
R/W
¾
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3~2
Bit 1~0
START: start the A/D conversion
0®1®0 : start
0®1 : reset the A/D converter and set EOCB to ²1²
This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and
then cleared low again, the A/D converter will initiate a conversion process. When the bit is set
high the A/D converter will be reset.
EOCB: End of A/D conversion flag
0: A/D conversion ended
1: A/D conversion in progress
This read only flag is used to indicate when an A/D conversion process has completed. When
the conversion process is running the bit will be high.
ADOFF : A/D module power on/off control bit
0: ADC module power on
1: ADC module power off
This bit controls the power to the A/D internal function. This bit should be cleared to zero to
enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing
the device power consumption. As the A/D converter will consume a limited amount of power,
even when not executing a conversion, this may be an important consideration in power sensitive
battery powered applications.
Note: 1. it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving
power.
2. ADOFF=1 will power down the ADC module.
ADRFS: A/D data format control bit
0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4
1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0
This bit controls the format of the 12-bit converted A/D value in the two A/D data registers.
Details are provided in the A/D data register section.
unimplemented, read as ²0²
ACS1, ACS0: Select A/D channel (when ACS4 is ²0²)
00: AN0
01: AN1
10: AN2
11: AN3
Rev. 1.40
75
November 22, 2016