HT66F016 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F016' PDF : 116 Pages View PDF
HT66F016/HT66F017/HT68F016/HT68F017
HT66F016R/HT66F017R/HT68F016R/HT68F017R
fSYS
1MHz
2MHz
4MHz
8MHz
12MHz
ADCK2,
ADCK1,
ADCK0
= 000
(fSYS)
1ms
500ns
250ns*
125ns*
83ns*
ADCK2,
ADCK1,
ADCK0
= 001
(fSYS/2)
2ms
1ms
500ns
250ns*
167ns*
ADCK2,
ADCK1,
ADCK0
= 010
(fSYS/4)
4ms
A/D Clock Period (tADCK)
ADCK2,
ADCK1,
ADCK0
= 011
(fSYS/8)
ADCK2,
ADCK1,
ADCK0
= 100
(fSYS/16)
8ms
16ms*
ADCK2,
ADCK1,
ADCK0
= 101
(fSYS/32)
32ms*
2ms
1ms
500ns
333ns*
4ms
2ms
1ms
667ns
8ms
4ms
2ms
1.33ms
16ms*
8ms
4ms
2.67ms
A/D Clock Period Examples
ADCK2,
ADCK1,
ADCK0
= 110
(fSYS/64)
64ms*
32ms*
16ms*
8ms
5.33ms
ADCK2,
ADCK1,
ADCK0
= 111
Undefined
Undefined
Undefined
Undefined
Undefined
Controlling the power on/off function of the A/D con-
verter circuitry is implemented using the ADOFF bit in
the ADCR0 register. This bit must be zero to power on
the A/D converter. When the ADOFF bit is cleared to
zero to power on the A/D converter internal circuitry a
certain delay, as indicated in the timing diagram, must
be allowed before an A/D conversion is initiated. Even if
no pins are selected for use as A/D inputs by clearing
the ACE3~ACE0 bits in the ACERL register, if the
ADOFF bit is zero then some power will still be con-
sumed. In power conscious applications it is therefore
recommended that the ADOFF is set high to reduce
power consumption when the A/D converter function is
not being used.
The reference voltage supply to the A/D Converter can
be supplied from either the positive power supply pin,
VDD, or from an external reference sources supplied on
pin VREF. The desired selection is made using the
VREFS bit. As the VREF pin is pin-shared with other
functions, when the VREFS bit is set high, the VREF pin
function will be selected and the other pin functions will
be disabled automatically.
A/D Input Pins
All of the A/D analog input pins are pin-shared with the
I/O pins on PA3~PA0 as well as other functions. The
ACE3~ ACE0 bits in the ACERL register determines
whether the input pins are setup as A/D converter ana-
log inputs or whether they have other functions. If the
ACE3~ ACE0 bits for its corresponding pin is set high
then the pin will be setup to be an A/D converter input
and the original pin functions disabled. In this way, pins
can be changed under program control to change their
function between A/D inputs and other functions. All
pull-high resistors, which are setup through register pro-
gramming, will be automatically disconnected if the pins
are setup as A/D inputs. Note that it is not necessary to
first setup the A/D pin as an input in the PAC port control
register to enable the A/D input as when the ACE3~
ACE0 bits enable an A/D input, the status of the port
control register will be overridden.
The A/D converter has its own reference voltage pin
VREF however the reference voltage can also be sup-
plied from the power supply pin, a choice which is made
through the VREFS bit in the ADCR1 register. The ana-
log input values must not be allowed to exceed the value
of VREF.
P A 0 /A N 0
P A 3 /A N 3
1 .2 5 V
A C S 4,A C S 1~A C S 0
In p u t V o lta g e
B u ffe r
V 125E N
1 2 - b it A D C
V REF
VR EFS
VDD
P A 1 /V R E F
B andgap
R e fe re n c e
V o lta g e
A/D Input Structure
Summary of A/D Conversion Steps
The following summarises the individual steps that
should be executed in order to implement an A/D con-
version process.
· Step 1
Select the required A/D conversion clock by correctly
programming bits ADCK2~ADCK0 in the ADCR1 reg-
ister.
· Step 2
Enable the A/D by clearing the ADOFF bit in the
ADCR0 register to zero.
· Step 3
Select which channel is to be connected to the internal
A/D converter by correctly programming the ACS4
and ACS1~ACS0 bits which are also contained in the
ADCR1 and ADCR0 registers.
· Step 4
Select which pins are to be used as A/D inputs and
configure them by correctly programming the
ACE3~ACE0 bits in the ACERL register.
Rev. 1.40
78
November 22, 2016
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