HT66F016/HT66F017/HT68F016/HT68F017
HT66F016R/HT66F017R/HT68F016R/HT68F017R
· ADCR1 Register
Bit
7
6
5
4
3
2
1
0
Name
ACS4 V125EN
¾
VREFS
¾
ADCK2 ADCK1 ADCK0
R/W
R/W
R/W
¾
R/W
¾
R/W
R/W
R/W
POR
0
0
¾
0
¾
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2~0
ACS4: select internal 1.25V as ADC input control
0: disable
1: enable
This bit enables 1.25V to be connected to the A/D converter. The V125EN bit must first have
been set to enable the bandgap circuit 1.25V voltage to be used by the A/D converter. When the
ACS4 bit is set high, the bandgap 1.25V voltage will be routed to the A/D converter and the other
A/D input channels disconnected.
V125EN: internal 1.25V control
0: disable
1: enable
This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit
is set high the bandgap voltage 1.25V can be used by the A/D converter. If 1.25V is not used by
the A/D converter and the LVR/LVD function is disabled then the bandgap reference circuit will be
automatically switched off to conserve power. When 1.25V is switched on for use by the A/D
converter, a time tBG should be allowed for the bandgap circuit to stabilise before implementing
an A/D conversion.
unimplemented, read as ²0²
VREFS: selecte ADC reference voltage
0: internal ADC power
1: VREF pin
This bit is used to select the reference voltage for the A/D converter. If the bit is high, then the
A/D converter reference voltage is supplied on the external VREF pin. If the pin is low, then the
internal reference is used which is taken from the power supply pin VDD. When the A/D
converter reference voltage is supplied on the external VREF pin which is pin-shared with other
functions, all of the pin-shared functions except VREF on this pin are disabled.
unimplemented, read as ²0²
ADCK2, ADCK1, ADCK0: select ADC clock source
000: fSYS
001: fSYS/2
010: fSYS/4
011: fSYS/8
100: fSYS/16
101: fSYS/32
110: fSYS/64
111: undefined
These three bits are used to select the clock source for the A/D converter.
Rev. 1.40
76
November 22, 2016