LH28F008SC View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F008SC' PDF : 38 Pages View PDF
LH28F008SC
8M (1M × 8) Flash Memory
DC CHARACTERISTICS (Continued)
SYM.
PARAMETER
VCC = 3.3 V
MIN.
MAX.
VCC = 5 V
MIN.
MAX.
UNIT TEST CONDITIONS NOTE
VIL Input Low Voltage
-0.5
0.8
-0.5
0.8
V
7
VIH Input High Voltage
2.0
VCC + 0.5
2.0
VCC + 0.5 V
7
VOL Output Low Voltage
0.4
0.45
V
VCC = VCC MIN.,
IOL = 5.8 mA
3, 7
VOH1
Output High Voltage
(TTL)
2.4
2.4
V
VCC = VCC MIN.,
IOH = 2.5 mA
3, 7
VOH2
Output High Voltage
(CMOS)
0.85 VCC
VCC - 0.4
0.85 VCC
VCC - 0.4
V
VCC = VCC MIN.,
IOH = 2.5 µA
4, 7
V
VCC = VCC MIN.,
IOH = 100 µA
VPPLK
VPP Lockout during
Normal Operations
1.5
1.5
V
VPPH1
VPP during Byte Write,
Block Erase, or Lock-
3.0
3.6
V
Bit Operations
VPPH2
VPP during Byte Write,
Block Erase, or Lock-
4.5
5.5
4.5
5.5
V
Bit Operations
VPPH3
VPP during Byte Write,
Block Erase, or Lock-
11.4
12.6
11.4
12.6
V
Bit Operations
VLKO VCC Lockout Voltage
2.0
2.0
V
VHH RP » Unlock Voltage
Set Master Lock-Bit
11.4
12.6
11.4
12.6
V Override Master and 8
Block Lock-Bit
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact
SHARP’s Application Support Hotline or your local sales office for information about typical specifications.
2. ICCWS and ICCES are specified with the device de-selected. If read or byte written while in erase suspend mode, the device’s current
draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively.
3. Includes RY »/BY ».
4. Block erases, byte writes, and lock-bit configurations are inhibited when VPP ≤ VPPLK, and not guaranteed in the range between VPPLK
(MAX.) and VPPH1(MIN.), between VPPH1(MAX.) and VPPH2 (MIN.), between VPPH2 (MAX.) and VPPH3 (MIN.), and above VPPH3 (MAX.).
5. Automatic Power Savings (APS) reduces typical ICCR to 1mA at 5 V VCC and 3 mA at 3.3 V VCC in static operation.
6. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH.
7. Sampled, but not 100% tested.
8. Master lock-bit set operations are inhibited when RP » = VIH. Block lock-bit configuration operations are inhibited when the master lock
bit is set and RP » = VIH. Block erases and byte writes are inhibited when the corresponding block-lock bit is set and RP» = VIH.
Block erase, byte write, and lock-bit configuration operations are not guaranteed with VIH < RP » < VHH.
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