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PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation

Part Name
Description
MFG CO.
PI7C7100
PERICOM
Pericom Semiconductor Corporation PERICOM
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566
12.2 Secondary Interface
S1_CBE[3:0]#
S2_CBE[3:0]#
Command
0000
Interrupt
Acknowledge
0001
Special Cycle
0010
I/O Read
0011
I/O Write
0100
Reserved
0101
Reserved
0110
Memory Read
0111
Memory Write
1000
Reserved
1001
Reserved
1010
Configuration
Read
1011
Configuration
Write
1100
1101
1110
1111
Memory Read
Multiple
Dual Address
Cycle
Memory Read
Line
Memory Write
& Invalidate
Action
Ignore.
Do not claim. Ignore.
Same as primary interface.
Same as I/O read.
-----
-----
Same as primary interface.
Same as Memory Read.
-----
-----
Ignore.
I. Type 0 configuration write: Ignore.
II. Type 1 configuration write (not special cycle request): Ignore.
III. Configuration write as special cycle request
(device = 1Fh, function = 7h):
1. If the target bus is the bridge's primary bus: claim and pass through
as a special cycle.
2. If the target bus is neither the primary bus nor is it in range of buses
defined by the bridge's secondary and subordinate bus registers: claim
and pass through unchanged as a type 1 configuration write.
3. If the target bus is not the bridge's primary bus: but is in range of buses
defined by the bridge's secondary and subordinate bus registers: Ignore.
Same as Memory Read
Not Supported
Same as Memory Read
Same as Memory Read
54
09/18/00 Rev 1.1
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