ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566
13.2 Configuration Register 2
31-24
23-16
15-8
7-0
Address
Device ID
Vendor ID
00h
Status
Command
04h
Class Code
Revision ID
08h
Reserved
Header Type
Primary Latency Timer Cache Line Size 0Ch
Reserved
10h-14h
Secondary Latency
Timer
Subordinate Bus
Number
Secondary Bus
Number
Primary Bus 18h
Number
Secondary Status
I/O Limit
I/O Base
1Ch
Memory Limit
Memory Base
20h
Prefetchable Memory Limit
Reserved
Prefetchable Memory Base
24h
28h-2Ch
I/O Limit Upper 16 Bits
Subsystem ID
I/O Base Upper 16 Bits
30h
Subsystem Vendor ID
34h
Bridge Control
Reserved
Interrupt Pin
38h
Reserved
3Ch
Arbiter Control
Diagnostic Control
Chip Control
40h
Primary Prefetchable Memory Limit
Primary Prefetchable Memory Base
44h
Reserved
48h-60h
Reserved
64h
Reserved
Reserved
Secondary Clock Control
68h
Reserved
6Ch
Non-Posted Memory Limit
Reserved
Non-Posted Memory Base
70h
Reserved
74h
Reserved
78h
Sampling Timer
7Ch
Secondary Successful I/O read count
80h
Secondary Successful I/O write count
84h
Secondary Successful memory read count
88h
Secondary Successful memory write count
8Ch
Reserved
90h
Reserved
94h
Reserved
98h
Reserved
9Ch
Reserved
A0h-FFh
56
09/18/00 Rev 1.1