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PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation

Part Name
Description
MFG CO.
PI7C7100
PERICOM
Pericom Semiconductor Corporation PERICOM
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677
13.2.1 Config Register 1 or 2: Vendor ID Register (read only, bit 15-0; offset 00h)
Pericom ID is 12D8h.
13.2.2 Config Register 1: Device ID Register (read only, bit 31-16; offset 00h)
Hardwired to 1B59h (S1)
13.2.3 Config Register 2: Device ID Register (read only, bit 31-16; offset 00h)
Hardwired to 1B5Ah (S2)
13.2.4 Configuration Register 1: Command Register (bit 15-0; offset 04h)
Bit
Function
Type
Description
15-10
9
Reserved
Fast Back to
Back Enable
R/O
Reset to '000000'
R/W
Controls bridge's ability to generate fast back-to-back transactions
to different devices on the primary interface.
0 = no fast back to back transaction
1 = enable fast back to back transaction
Reset to 0
SERR# Enable
8
R/W
Controls the enable for the P_SERR# pin.
0=disable the P_SERR# driver
1 = enable the P_SERR# driver
Reset to 0
7
Wait Cycle Control
Parity Error Enable
6
R/O
No data stepping supported.
Reset to 0
R/W
Controls bridge's response to parity errors.
0 = ignore any parity errors
1 = normal parity checking performed
Reset to 0
VGA Palette Snoop Enable R/W
5
Controls bridge's response to VGA compatible palette accesses.
0 = ignore VGA palette accesses on the primary interface
1 = enable response to VGA palette writes on the primary interface
(I/O address AD[9:0] = 3C6h, 3C8h and 3C9h)
Reset to 0
4
Memory Write and
Invalidate Enable
R/O
Memory Write and Invalidate not supported
Reset to 0
3
Special Cycle Enable
Bus Master Enable
2
Memory Space Enable
1
R/O
No special cycle implementation
Reset to 0
R/W
Controls bridge's ability to operate as a master on the primary
interface.
0 = do not initiate transaction on the primary interface and
disable response to memory or I/O transactions on secondary
interface
1 = enable the bridge to operate as a master on the primary
interface
Reset to 0
R/W
Controls bridge's response to memory accesses on the primary
interface.
0 = ignore all memory transaction
1 = enable response to memory transaction
Reset to 0
I/O Space Enable
0
R/W
Controls bridge's response to I/O accesses on the primary interface.
0 = ignore I/O transaction
1 = enable response to I/O transaction
Reset to 0
Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear
57
09/18/00 Rev 1.1
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