PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677
13. Configuration Registers
As PI7C7100 supports two secondary interfaces, it has two sets of configuration registers which are almost identical
and accessed through different function numbers. The description below is for one set only.
PCI configuration defines a 64-byte space (configuration header) to define various attributes of the PCI-to-PCI Bridge
as shown below. All of the registers in bold type are required by the PCI specification and are implemented in this
bridge. The others are available for use as control registers for the device. There are two configuration registers:
Configuration Register 1 and Configuration Register 2 corresponding to Secondary bus 1 and Secondary bus 2
interfaces respectively. Also, the configuration for the primary interface is implemented through the Configuration
Register 1.
13.1 Configuration Register 1
31-24
23-16
15-8
7-0
Address
Device ID
Vendor ID
00h
Status
Command
04h
Class Code
Revision ID
08h
Reserved
Header Type
Primary Latency Timer
Cache Line Size 0Ch
Reserved
10h-14h
Secondary Latency
Timer
Subordinate Bus
Number
Secondary Bus
Number
Primary Bus
18h
Number
Secondary Status
I/O Limit
I/O Base
1Ch
Memory Limit
Memory Base
20h
Prefetchable Memory Limit
Prefetchable Memory Base
24h
Reserved
28h-2Ch
I/O Limit Upper 16 Bits
I/O Base Upper 16 Bits
30h
Subsystem ID
Subsystem Vendor ID
34h
Reserved
38h
Bridge Control
Interrupt Pin
Reserved
3Ch
Arbiter Control
Diagnostic Control
Chip Control
40h
Primary Prefetchable Memory Limit
Primary Prefetchable Memory Base
44h
Reserved
48h-60h
Reserved
P_SERR# Event
64h
Disable
Reserved
Reserved
Secondary Clock Control
68h
Reserved
6Ch
Non-Posted Memory Limit
Non-Posted Memory Base
70h
Master Timeout Counter
Port Option
74h
Retry Counter
78h
Sampling Timer
7Ch
Secondary Successful I/O read count
80h
Secondary Successful I/O write count
84h
Secondary Successful memory read count
88h
Secondary Successful memory write count
8Ch
Primary Successful I/O read count
90h
Primary Successful I/O write count
94h
Primary Successful memory read count
98h
Primary Successful memory write count
9Ch
Reserved
A0h-FFh
55
09/18/00 Rev 1.1
Share Link: 
