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PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation

Part Name
Description
MFG CO.
PI7C7100
PERICOM
Pericom Semiconductor Corporation PERICOM
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677
13.2.6 Configuration Register 1 or 2: Status Register (for primary bus, bits 31-16; offset 04h)
Bit
Function
Type
Description
31 Detected Parity Error
R/WC Should be set whenever a parity error is detected regardless of the
state of bit 6 of the command register.
Reset to 0
30 Signaled System Error
R/WC Should be set whenever P_SERR# is asserted.
Reset to 0
29 Received Master Abort
R/WC Set to '1' (by a master) when transactions are terminated
with Master Abort.
Reset to 0
28 Received Target Abort
R/WC Set to '1' (by a master device) when transactions are terminated
with Target Abort.
Reset to 0
27 Signaled Target Abort
R/WC Should be set (by a target device) whenever a Target Abort
cycle occurs.
Reset to 0
26-25 DEVSEL Timing
R/O Medium DEVSEL# timing.
Reset to '01'
24 Data Parity Error Detected R/WC It is set when the following conditions are met:
1. P_PERR# is asserted
2. Bit 6 of Command Register is set
Reset to 0
23 Fast Back to Back Capable R/O Fast back-to-back write capable on primary side.
Reset to 1
22 Reserved
R/O Reset to 0
21 Reserved
R/O Reset to 1
20 Capabilities List
R/O Capabilities List is not supported.
Reset to 0
19-16 Reserved
R/O Reset to 0
Note: R/W - Read/Write; R/O - Read Only; R/WC - Read/Write1 to clear.
59
09/18/00 Rev 1.1
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