ST10F167 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F167' PDF : 69 Pages View PDF
ST10F167
V - FLASH MEMORY
The ST10F167 provides 128K Byte of on-chip,
electrically erasable and re-programmable Flash
EPROM. The flash memory is organized in 32 bit
wide blocks. Double Word instructions can be
fetched in one machine cycle. The flash memory
can be used for both code and data storage. It is
organised into four banks of sizes 8K, 24K, 48K
and 48K Byte. Each of these banks can be erased
independently. This prevents unnecessary re-pro-
gramming of the whole flash memory when only
partial re-programming is required.
The first 32K Byte of the FLASH memory are
located in segment 0 (0h to 007FFFh) during reset,
and include the reset and interrupt vectors. The
rest of the FLASH memory is mapped in segments
1 and 2 (018000h to 02FFFFh). For flexibility, the
first 32K Byte of the FLASH memory may be
remapped to segment 1 (010000h to 017FFFh)
during initialization. This allows the interrupt vec-
tors to be programmed from the external memory,
while retaining the common routines and constants
that are programmed into the FLASH memory.
Table 2 : Flash memory bank addresses
Bank
Addresses (Segment 0)
Size
(Byte)
0 000000h to 07FFFh
48K
1 and 018000h to 01BFFFh
48K
2 01C000h to 027FFFh
24K
3 028000h to 02DFFFh
8K
02E000h to 02FFFFh
V.1 - Flash programming and erasing
The FLASH memory is programmed using the
PRESTO F Program Write algorithm. Erasure of
the FLASH memory is performed in the program
mode using the PRESTO F Erase algorithm.
Timing of the Write/Erase cycles is automatically
generated by a programmable timer and comple-
tion is indicated by a flag. A second flag indicates
that the VPP voltage was correct for the whole pro-
gramming cycle. This guarantees that a good
write/erase operation has been carried out.
Table 3 : Flash Parameters
Parameter Units Min Typical Max
Word
Programming
Time
Bank Erasing
Time
Endurance
µsec
sec
cycles
12.8
12.8
0.5
1000
1250
30
Flash VPP
volts
11.4
12.6
V.2 - Flash Control Register (FCR)
In the standard operation mode, the FLASH mem-
ory can be accessed in the same way as the nor-
mal mask-programmable on-chip ROM. All
appropriate direct and indirect addressing modes
can be used for reading the FLASH memory.
All programming or erase operations are con-
trolled via a 16-bit register, the FCR. The FCR is
not an SFR or GPR. To prevent inadvertent writing
to the FLASH memory, the FCR is locked and
inactive during the standard operation mode. The
FLASH memory writing mode must be entered
before a valid access to the FCR is provided. This
is done via a special key code instruction
sequence.
The FCR is virtually mapped into the active
address space of the Flash memory. It can only be
accessed with direct 16-bit (mem) addressing
modes. Since the FCR is neither byte, nor
bit-addressable, only word operand instructions
can be used for FCR accesses. By default, the
FCR can be accessed with any even address from
000000h to 07FFFEh and 018000h to 02FFFEh.
If the first 32K byte Block of the FLASH memory is
mapped to segment 1, the corresponding even
FCR addresses are 010000h to 017FFEh. Note
that DPP referencing and DPP contents must be
considered for FCR accesses. If an FCR access is
attempted via an odd address, an illegal operand
access hardware trap will occur.
FCR Flash Control Register: Reset Condition:
0000h (Read).
12/61
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