ST10F167 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F167' PDF : 69 Pages View PDF
ST10F167
VIII - INTERRUPT SYSTEM
With an interrupt response time from 250ns to
600ns (in the case of internal program execution),
the ST10F167 reacts quickly to the occurrence of
non-deterministic events
The architecture of the ST10F167 supports
several mechanisms for fast and flexible response
to service requests that can be generated from
various sources internal or external to the
microcontroller. Any of these interrupt requests
can be programmed to being serviced by the
Interrupt Controller or by the Peripheral Event
Controller (PEC).
In a standard interrupt service, program execution
is suspended and a branch to the interrupt vector
table is performed. For a PEC service, just one
cycle is ‘stolen’ from the current CPU activity. A
PEC service is a single byte or word data transfer
between any two memory locations with an addi-
tional increment of either the PEC source or the
destination pointer. An individual PEC transfer
counter is decremented for each PEC service,
except for the continuous transfer mode. When
this counter reaches zero, a standard interrupt is
performed to the corresponding source related
vector location. PEC services are suited to, for
example, the transmission or reception of blocks
of data. The ST10F167 has 8 PEC channels,
Table 5 : List of interrupt sources
each of which offers fast interrupt-driven data
transfer capabilities.
A separate control register which contains an
interrupt request flag, an interrupt enable flag and
an interrupt priority bitfield, exists for each of the
possible interrupt sources. Via its related register,
each source can be programmed to one of sixteen
interrupt priority levels. Once having been
accepted by the CPU, an interrupt service can
only be interrupted by a higher prioritized service
request. For the standard interrupt processing,
each of the possible interrupt sources has a dedi-
cated vector location.
Fast external interrupt inputs are provided to ser-
vice external interrupts with high precision
requirements. These fast interrupt inputs, feature
programmable edge detection (rising edge, falling
edge or both edges).
Software interrupts are supported by means of the
‘TRAP’ instruction in combination with an individ-
ual trap (interrupt) number.
Table 5 shows all the available ST10F167 inter-
rupt sources and the corresponding hard-
ware-related interrupt flags, vectors, vector
locations and trap (interrupt) numbers.
Source of Interrupt or PEC
Service Request
CAPCOM Register 0
CAPCOM Register 1
CAPCOM Register 2
CAPCOM Register 3
CAPCOM Register 4
CAPCOM Register 5
CAPCOM Register 6
CAPCOM Register 7
CAPCOM Register 8
CAPCOM Register 9
CAPCOM Register 10
CAPCOM Register 11
CAPCOM Register 12
CAPCOM Register 13
CAPCOM Register 14
CAPCOM Register 15
CAPCOM Register 16
CAPCOM Register 17
Request
Flag
CC0IR
CC1IR
CC2IR
CC3IR
CC4IR
CC5IR
CC6IR
CC7IR
CC8IR
CC9IR
CC10IR
CC11IR
CC12IR
CC13IR
CC14IR
CC15IR
CC16IR
CC17IR
Enable
Flag
CC0IE
CC1IE
CC2IE
CC3IE
CC4IE
CC5IE
CC6IE
CC7IE
CC8IE
CC9IE
CC10IE
CC11IE
CC12IE
CC13IE
CC14IE
CC15IE
CC16IE
CC17IE
Interrupt
Vector
CC0INT
CC1INT
CC2INT
CC3INT
CC4INT
CC5INT
CC6INT
CC7INT
CC8INT
CC9INT
CC10INT
CC11INT
CC12INT
CC13INT
CC14INT
CC15INT
CC16INT
CC17INT
Vector
Location
00’0040h
00’0044h
00’0048h
00’004Ch
00’0050h
00’0054h
00’0058h
00’005Ch
00’0060h
00’0064h
00’0068h
00’006Ch
00’0070h
00’0074h
00’0078h
00’007Ch
00’00C0h
00’00C4h
Trap
Number
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
30h
31h
18/61
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