ST10F167 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F167' PDF : 69 Pages View PDF
ST10F167
VI - EXTERNAL BUS CONTROLLER
All of the external memory accesses are per-
formed by the on-chip External Bus Controller
(EBC). It can be programmed either to single chip
mode when no external memory is required, or to
one of four different external memory access
modes:
– 16-/18-/20-/24-bit Addresses, 16-bit Data,
Demultiplexed
– 16-/18-/20-/24-bit Addresses, 16-bit Data,
Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data,
Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data,
Demultiplexed
In the demultiplexed bus modes, addresses are
output on PORT1 and data is input/output on
PORT0. In the multiplexed bus modes both
addresses and data use PORT0 for input/output.
Important timing characteristics of the external
bus interface (Memory Cycle Time, Memory
Tri-State Time, Length of ALE and Read/Write
Delay) have been made programmable. This
gives the choice of a wide range of external of
memories and external peripherals. In addition,
different address ranges may be accessed with
different bus characteristics. Up to 5 external CS
signals (4 windows plus default) can be generated
in order to save external glue logic. Access to very
slow memories is supported via a particular
‘Ready’ function. A HOLD/HLDA protocol is avail-
able for bus arbitration.
For applications which require less than 16M Byte
of external memory space, this address space
can be restricted to 1M Byte, 256K Byte or to
64K Byte. In this case Port 4 outputs four, two or
no address lines. If an address space of 16M Byte
is used, it outputs all 8 address lines.
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