ST10F167 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F167' PDF : 69 Pages View PDF
ST10F167
VIII - INTERRUPT SYSTEM (continued)
The ST10F167 identifies and to processes
exceptions or error conditions that arise during
run-time, ‘Hardware Traps’. Hardware traps cause
an immediate non-maskable system reaction
which is similar to a standard interrupt service
(branching to a dedicated vector table location).
The occurrence of a hardware trap is additionally
signified by an individual bit in the trap flag regis-
ter (TFR). Except when another higher prioritized
trap service is in progress, a hardware trap will
interrupt any current program execution. In turn,
hardware trap services can normally not be inter-
rupted by standard or PEC interrupts
Table 6 shows all of the possible exceptions or
error conditions that can arise during run-time.
Table 6 : Exceptions or error conditions that can arise during run time
Exception Conditi on
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps:
Undefined Opcode
Protected Instruction Fault
Illegal Word Operand Access
Illegal Instruction Access
Illegal External Bus Access
Reserved
Software Traps:
TRAP Instruction
RESET
00’0000h
00h
III
RESET
00’0000h
00h
III
RESET
00’0000h
00h
III
NMI
NMITRAP
00’0008h
02h
II
S TKO F
STOTR AP
00’0010h
04h
II
STKUF
STUTRAP
00’0018h
06h
II
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
[2Ch –3Ch]
Any
[00’0000h–
00’01FCh]
in steps of 4h
0Ah
0Ah
0Ah
0Ah
0Ah
[0Bh – 0Fh]
Any
[00h – 7Fh]
I
Current
CPU
Priority
20/61
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