ST10F167 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST10F167

16-BIT MCU WITH 128K BYTE FLASH MEMORY

STMicroelectronics 

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ST10F167

VIII - INTERRUPT SYSTEM (continued)

Table 5 : List of interrupt sources

Source of Interrupt or PEC

Service Request

Request

Flag

Enable

Flag

Interrupt

Vector

Vector

Location

Trap

Number

CAPCOM Register 18

CC18IR

CC18IE

CC18INT

00’00C8h

32h

CAPCOM Register 19

CC19IR

CC19IE

CC19INT

00’00CCh

33h

CAPCOM Register 20

CC20IR

CC20IE

CC20INT

00’00D0h

34h

CAPCOM Register 21

CC21IR

CC21IE

CC21INT

00’00D4h

35h

CAPCOM Register 22

CC22IR

CC22IE

CC22INT

00’00D8h

36h

CAPCOM Register 23

CC23IR

CC23IE

CC23INT

00’00DCh

37h

CAPCOM Register 24

CC24IR

CC24IE

CC24INT

00’00E0h

38h

CAPCOM Register 25

CC25IR

CC25IE

CC25INT

00’00E4h

39h

CAPCOM Register 26

CC26IR

CC26IE

CC26INT

00’00E8h

3Ah

CAPCOM Register 27

CC27IR

CC27IE

CC27INT

00’00ECh

3Bh

CAPCOM Register 28

CC28IR

CC28IE

CC28INT

00’00E0h

3Ch

CAPCOM Register 29

CC29IR

CC29IE

CC29INT

00’0110h

44h

CAPCOM Register 30

CC30IR

CC30IE

CC30INT

00’0114h

45h

CAPCOM Register 31

CC31IR

CC31IE

CC31INT

00’0118h

46h

CAPCOM Timer 0

T0IR

T0IE

T0INT

00’0080h

20h

CAPCOM Timer 1

T1IR

T1IE

T1INT

00’0084h

21h

CAPCOM Timer 7

T7IR

T7IE

T7INT

00’00F4h

3Dh

CAPCOM Timer 8

T8IR

T8IE

T8INT

00’00F8h

3Eh

GPT1 Timer 2

T2IR

T2IE

T2INT

00’0088h

22h

GPT1 Timer 3

T3IR

T3IE

T3INT

00’008Ch

23h

GPT1 Timer 4

T4IR

T4IE

T4INT

00’0090h

24h

GPT2 Timer 5

T5IR

T5IE

T5INT

00’0094h

25h

GPT2 Timer 6

T6IR

T6IE

T6INT

00’0098h

26h

GPT2 CAPREL Register

CRIR

CRIE

CRINT

00’009Ch

27h

A/D Conversion Complete

ADCIR

ADCIE

ADCINT

00’00A0h

28h

A/D Overrun Error

ADEIR

ADEIE

ADEINT

00’00A4h

29h

ASC0 Transmit

S0TIR

S0TIE

S0TINT

00’00A8h

2Ah

ASC0 Transmit Buffer

S0TBIR

S0TBIE

S0TBINT

00’011Ch

47h

ASC0 Receive

S0RIR

S0RIE

S0RINT

00’00ACh

2Bh

ASC0 Error

S0EIR

S0EIE

S0EINT

00’00B0h

2Ch

SSC Transmit

SCTIR

SCTIE

SCTINT

00’00B4h

2Dh

SSC Receive

SCRIR

SCRIE

SCRINT

00’00B8h

2Eh

SSC Error

SCEIR

SCEIE

SCEINT

00’00BCh

2Fh

PWM Channel 0...3

PWMIR

PWMI E

PWMINT

00’00FCh

3Fh

CAN Interface

XP0IR

XP0IE

XP0INT

00’0100h

40h

X-Peripheral Node

XP1IR

XP1IE

XP1INT

00’0104h

41h

X-Peripheral Node

XP2IR

XP2IE

XP2INT

00’0108h

42h

PLL Unlock

XP3IR

XP3IE

XP3INT

00’010Ch

43h

Note Two X-Peripheral nodes can accept interrupt requests from integrated X-Bus peripherals. Nodes where no X-Peripherals are

connected may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.

19/61

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