ST10F167 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F167' PDF : 69 Pages View PDF
ST10F167
VII - CENTRAL PROCESSING UNIT (CPU)
Figure 6 : CPU Block Diagram
256K Byte
Flash
memory
32
CPU
SP
STKO V
STKUN
Exec. Unit
Instr. Ptr
Instr. Reg
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Data Pg. Ptrs
MDH
MLD
Mul./Div.-HW
Bit-Mask Gen.
ALU
16-Bit
Barrel-Shift
CP
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Code Seg. Ptr.
R15
General
Purpose
Registers
R0
Internal
RAM
2K Byte
Bank
n
Bank
i
16
Bank
16
0
The CPU includes a 4-stage instruction pipeline, a
16-bit arithmetic and logic unit (ALU). Dedicated
SFRs have been added for a separate multiply
and divide unit, a bit-mask generator and a barrel
shifter.
Most of the ST10F167’s instructions can be exe-
cuted in one instruction cycle which requires
100ns at 20MHz CPU clock. For example, shift
and rotate instructions are always processed in
one machine cycle independent of the number of
bits to be shifted. All multiple-cycle instructions
have been optimized for speed: branches in 2
cycles, a 16 X 16 bit multiplication in 5 cycles and
a 32-/16 bit division in 10 cycles. The ‘Jump
Cache’ pipeline optimization, reduces the execu-
tion time of repeatedly performed jumps in a loop,
from 2 cycles to 1 cycle.
The CPU includes an actual register context. This
consists of up to 16 Wordwide GPRs which are
physically allocated within the on-chip RAM area.
A Context Pointer (CP) register determines the
base address of the active register bank to be
accessed by the CPU at a time. The number of
register banks is only restricted by the available
internal RAM space. For easy parameter passing,
a register bank may overlap others.
A system stack of up to 2048 Byte is provided as a
storage for temporary data. The system stack is
allocated in the on-chip RAM area, and it is
accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and
STKUN, are implicitly compared against the stack
pointer value upon each stack access for the
detection of a stack overflow or underflow.
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