ST10F167 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F167' PDF : 69 Pages View PDF
ST10F167
V - FLASH MEMORY (continued)
Table 4 : Flash control register bit definition
Bit number & name
Description
b15 = FWMSET
Flash Writing Mode Set.
b14-b10
b9-b8 = BE0,1
Bank erase select.
b7 = WDWW
Word/double word write.
b6-b5 = CKCTL0,1
Flash Timer Clock Con-
trol.
b4 = VPPRIV
VPP Revelation bit.
b3 = FCVPP
Flash VPP control bit.
b2 = FBUSY
Flash busy bit.
b2 = RPROT
Protection enable bit.
b1 = FEE
Flash erase/program
selection.
b0 = FWE
Flash write/read enable.
This bit is set to ”1” automatically once the Flash writing mode is entered. To exit from the
Flash writing mode, FWMSET must be set to ”0”. Since only word values can be written to
FCR, care must be taken that FWMSET is not cleared inadvertently. Therefore, for any
command written to FCR (except for the return to the Flash standard mode), FWMSET
must be set to ”1”. Reset condition of FWMSET is ”0”.
These bits are reserved for future development, they must be written to ”0”.
Select the Flash memory bank to be erased. The physical addresses of bank 0 depends on
the which Flash memory map has been chosen. In Flash operating modes, other than the
erasing mode, these bits are not significant. At reset BE1,0 are set to ”00”.
Determines the word width used for programming operations: 16-bit (WDWW = 0) or 32-bit
(WDWW = ”1”). In Flash operation modes, other than the programming mode, this bit is not
significant. At reset, WDWW is set to “0”.
Control the width (TPRG) of the programming or erase pulses applied to the Flash memory
cells during the operation. TPRG varies in an inverse ratio to the clock frequency. To avoid
putting the Flash memory under critical stress conditions, the width of one single program-
ming or erase pulse and the programming or erase time, must not exceed defined values.
Thus the maximum number of programming or erase attempts, depends on the system
clock frequency. RESET state: 00.
Read-only bit reflects the state of the VPP voltage in the Flash writing mode. If VPPRIV is
set to ”0”, this indicates that VPP is below the threshold necessary for reliable programming.
The normal reaction to this indication is to check the VPP power supply and to then repeat
the intended operation. If the VPP voltage is above a sufficient margin, VPPRIV will be set to
”1”. The reset state of the VPPRIV bit depends on the state of the external VPP voltage at
the VPP pin.
Read-only bit indicates that the VPP voltage fell below the valid threshold value during a
Flash programming or erase operation. If FCVPP is set to ”1” after such an operation has
finished, it can mean that the operation was not successful. The VPP power supply should
be checked and the operation repeated. If FCVPP is set to ”0”, no critical discontinuity in
VPP occurred. At reset FCVPP is set to ”0”.
Read-only bit indicates that a Flash programming or erase operation is in progress. FBUSY
is set to ”1” by hardware, as soon as the programming or erase command is given. At reset
FBUSY is set to ”0”. Note that this bit position is also occupied by the write-only bit RPROT.
This bit set at ’1’, and ed with the OTP protection bit, disables any access to the Flash, by
instructions fetched from the external memory space, or from the internal RAM. This
write-only bit, is only significant if the general Flash memory protection is enabled. If the
protection is enabled, the setting of RPROT determines whether the Flash protection is
active (RPROT=”1”) or inactive (RPROT=”0”). RPROT is the only FCR bit which can be
modified even in the Flash standard operation mode, but only by an instruction executed
from the Flash memory itself. At reset, RPROT is set to ”1”. Note that this bit position is also
occupied by the read-only bit FBUSY.
Selects the Flash write operation to be performed: erase (FEE=”1”) or programming
(FEE=”0”). Together with bits FWE and FWMSET, bit FEE determined the operation mode
of the Flash memory. Note that setting bits FWE and FEE causes the corresponding Flash
operation mode to be selected but does not launch the execution of the selected operation.
If bit FWE was set to ”0”, the setting of FEE is insignificant. At reset, FEE is set to ”0”.
This bit determines whether FLASH write operations are enabled (FWE=1) or disabled
(FWE=0). By definition, a FLASH write operation can be either programming or erasure.
Together with bits FEE and FWMSET, bit FWE determines the operation mode of the Flash
memory. Note that setting bits FWE and FEE causes the corresponding Flash operation
mode to be selected but does not launch the execution of the selected operation. If bit FWE
was set to ”1”, any read access on a Flash memory location means a particular pro-
gram-verify or erase-verify read operation. Flash write operations are disabled at reset.
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