ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
ST18-AU1
5 INPUT SERIAL INTERFACE
The ST18-AU1 has two input serial interfaces (DIN0 and DIN1). The interfaces are multi-
format serial interfaces for inputting audio bitstreams. Supported formats include delayed
(I2S)/non-delayed, left/right justified, 16/18/20/24-bit word, polarity options in L/R clock and
input clock, and master/slave mode. They provide the serial to parallel conversion and transfer
the input data to the input buffer for further processing.
Data input interface 0 (DIN0) operates with an input FIFO which regulates the input data flow
transferred to the input buffer. Data input interface 1 (DIN1) operates in a similar way to DIN0
but it does not have an associated input FIFO.
5.1 Input serial interface registers
Each input serial interface has the following set of registers.
DIN0-1CR: Data in control register
On reset, all bits are cleared.
15 14 13 12 11 10 9 8
--------
7
6
5
4
3
Mas- Justi- De- WS_p CLK_
ter fied layed ol pol
2
1
WS
Bit
DINEN
WS
CLK_pol
WS_pol
Delayed
Function
Input interface enable
0
input interface disabled
1’
input interface enabled
Input word size
Bit1 Bit 0
0
0
0
1
1
0
1
1
Input word size
16 bit
18 bit
20 bit
24 bit
Clock polarity
0
data and WS change on Clk falling edge
1
data and WS change on Clk rising edge
Word size polarity
0
Left data word = WS low, Right data word = WS high
1
Left data word = WS high, Right data word = WS low
Delay inserted before first bit of data following transition of WS.
0
first bit of data occurs on transition of WS
1
first bit of data occurs with 1 Clk cycle delay relative to transition of
WS (I2S compatible).
0
DIN-
EN
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