ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
ST18-AU1
5.2 Input FIFO
Associated with input serial interface 0 (DIN0) is a 32 byte input FIFO. It is used for temporary
storage of incoming data during processing of packet headers or AC3/MPEG decoding. The
input FIFO provides the following:
• transfer of data to the input buffer on a word basis
• packet header processing when operating on PES
• detection of FIFO overflow and FIFO filled to a predefined level
5.2.1 Input FIFO registers
FIFOCR: Input FIFO control register
On reset, all bits are cleared. The FIFO is cleared and the formatter is set to the ‘empty’ state.
15 14 13 12 11 10 9
8
76543 2
10
- - - CLR_Fo - DIN0_IE - DREQ_
rm
N
SEL
FIFO_level
DMA_ DREQ -
mod _EN
Bit
DREQ_EN
DMA_mod
FIFO_level
DREQ_SEL
DIN0_IEN
CLR_Form
-
Function
DREQ enable
0
DREQ= 0
1
DREQ set according to FIFO threshold/full level
DMA mode
0
DMA request always enabled
1
DMA request enabled only when PDC not equal to 0 (PES
processing)
FIFO threshold level (MSB=7, LSB=3). Set FIFO filling level for IRQ/DREQ manage-
ment.
DREQ signal settings (if DREQ_EN = 1)
0
DREQ is asserted high when FIFO threshold is reached
1
DREQ is asserted high when FIFO is full (if DREQ_EN=1)
DIN0 interrupt enable
0
interrupt disabled
1’
interrupt enabled (when FIFO_THS = 1)
Set formatter empty (active only at write time of FIFOCR)
RESERVED, read as 0.
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