ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
6 INPUT AND OUTPUT BUFFERS
ST18-AU1
6.1 Input buffer
The input buffer is single port memory mapped on the Y space. Taking into account the
requirements for AC3 decoding and SPDIF transmitter, its size is 2048 words (16-bit). It Is
software defined and may be dynamically sized. Buffer overflow detection is provided.
The D950 reads the buffer using its circular addressing mode of operation.
The DMA controller cycles through the buffer for write word by word, using a cycle stealing
mechanism: 3 D950 cycles are needed for each 16-bit word transfer.
When the SPDIF transmitter is enabled, another DMA channel is assigned to retrieving
encoded samples.
6.2 Output buffer
The output buffer is single port memory mapped on the X space.
For 2 channel and 6 channel PCM output, the size of the output buffer is software defined and
can be dynamically sized.
The D950 cycles through the buffer for write by using its circular addressing mode of operation.
The DMA controller cycles through the buffer for read of one sample at a time (2 or 3 words,
depending on samples format), using a cycle stealing mechanism.
In 2 channel output mode, one DMA channel is used.
In 6 channel output mode, three DMA channels are used.
The DMA channel used must operate on “Level” mode.
Buffer underflow detection can be performed using on-chip dedicated resources.
6.2.1 Input and output buffer registers
BUFCR: Buffer control register
All bits are cleared on reset.
15 14 13 12 11 10
9
8
76543 2
1
0
- - - - - - UDF_OUT OVF_INB - - - - - UDF_ OVF_IN EN_B
BUF_IEN UF_IEN
mod BUF UF
Bit
EN_BUF
OVF_INBUF
Function
Enable input/output buffer logic
Input buffer overflow
0
INBUFOVF= ‘0’
1
INBUFOVF=INBUF_FULL
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