ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
ST18-AU1
UDF_mod
OVF_INBUF_IEN
UDF_OUTBUF_IEN
-
Output buffer underflow
0
OUTBUFUDF= ‘0’
1
OUTUFUDF=OUTBUF_EMPTY
Input buffer overflow interrupt enable
0
disable
1
enable
Output buffer underflow interrupt enable
0
disable
1
enable
RESERVED, Read as 0.
BUFSR: Buffer status register
All bits are cleared on reset.
15 14 13 12 11 10
9
8
76543210
- - - - - - OUTBUF INBUF_F - - - - - - - -
_EMPTY ULL
Bit
INBUF_FULL
OUTBUF_EMPTY
-
Function
Input buffer full. Set and reset by hardware.
Output buffer empty. Set and reset by hardware.
RESERVED, Read as 0.
INBUFRAR:Input buffer read address register
This register is not initialized on Reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RADD
Bit
RADD
Function
Reference address for Compare
OUTBUFWAR: Output buffer write address register
This register is not initialized on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WADD
Bit
WADD
Function
Reference address for Compare.
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