ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
ST18-AU1
Justified
Master
-
If number of Clk cycles between WS transitions is > n (= word size)
0
start justified: n bits read, starting from first bit:
just after WS transition if Delayed =’0’
with 1 clk cycle delay after WS transition if Delayed=’1’
1
end justified, end bit beein last bit received:
just before WS transition if Delayed =’0’
just after WS transition if Delayed =’1’
Master or slave operation
0
slave
1
master
NOTE: this bit must be defined before the input interface enable (DINEN) bit is set.
RESERVED, read as 0.
DIN0-1DIV: Data in division register
On reset, DIN0DIV value is set to 0.
15 14 13 12 11 10 9 8 7
6
5
4
3
2
1
0
--------
DINDIV
Bit
DINDIV
Function
MCLK_DIN divide factor
00000000’
1
00000001
2
.....
......
11111111
’510 ‘
fCLKDIN= fMCLK_DIN/2(DIN0DIV) if DIN0DIV /= ‘00000
RESERVED, read as 0.
DIN1DR: Data in output register
This 16-bit register contains the serial interface input data and is read by the D950.
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