ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
ST18-AU1
FIFOSR: Input FIFO status register
FIFO_FULL and FIFO_THR are cleared on reset.
15 14 13 12
11
10
9
8
76543210
- - - Form_e PDC_N FIFO_T FIFO_ FIFO_F - - - - - - - -
mpty ULL HR EMPTY ULL
Bit
FIFO_FULL
FIFO_EMPTY
FIFO_THR
PDC_NULL
Form_empty
-
Function
FIFO full: set and reset by hardware
FIFO empty: set and reset by hardware
FIFO threshold: set and reset by hardware
Set when PDC = 0, otherwise reset
Set when formatter empty, otherwise reset
RESERVED, read as 0.
FIFO_out: FIFO output data register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data
--------
Bit
Data
-
Function
Data (MSB=15, LSB=8)
RESERVED, read as 0.
FORM_out: Formatter output data register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DataH
DataL
Bit
Data L
Data H
Function
Data least significant byte
Data most significant byte
PDCR: Packet data count register
Cleared on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-----
PDC
Bit
PDC
-
Function
Packet data count value in bytes. Maximum count value is 2047.
RESERVED, read as 0.
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