XE8801A – SX8801R
4 Memory Mapping
4.1
Memory organisation
4-2
4.2
Quick reference data memory register map
4-2
4.2.1
Low power data registers (h0000-h0007)
4-3
4.2.2
System, clock configuration and reset configuration (h0010-h001F)
4-4
4.2.3
Port A (h0020-h0027)
4-4
4.2.4
Port B (h0028-h002F)
4-4
4.2.5
Port C (h0030-h0033)
4-5
4.2.6
Flash programming (h0038-003B)
4-5
4.2.7
Event handler (h003C-h003F)
4-5
4.2.8
Interrupt handler (h0040-h0047)
4-6
4.2.9
USRT (h0048-h004F)
4-7
4.2.10 UART (h0050-h0057)
4-7
4.2.11 Counter/Timer/PWM registers (h0058-h005F)
4-7
4.2.12 Acquisition chain registers (h0060-h0067)
4-8
4.2.13 Voltage multiplier (h007C)
4-8
4.2.14 Voltage Level Detector registers (h007E-h007F)
4-8
4.2.15 RAM (h0080-h027F)
4-8
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4-1