SX8801IRXXMLTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX8801IRXXMLTRT' PDF : 135 Pages View PDF
XE8801A – SX8801R
4.1 Memory organisation
The XE8801AM-SX8801R CPUs are built with Harvard architecture. Harvard architecture uses separate instruction
and data memories. The instruction bus and data bus are also separated. The advantage of such a structure is that
the CPU can get a new instruction and read/write data simultaneously. The circuit configuration is shown in Figure
4-1. The CPU has its 16 internal registers. The instruction memory has a capacity of 8192 22-bit instructions. The
data memory space has 8 low power registers, the peripheral register space and 512 bytes of RAM.
µF0hµ1FFFF
Instruction
memory
capacity:
8k x 22bit
0h0000
CPU
r0
r1
r2
r3
i0h
i0l
i1h
i1l
i2h
i2l
i3h
i3l
iph
ipl
stat
a
0h027F
RAM
capacity:
512 bytes
0h0080
0h007F
Peripheral
registers
0h0008
Low power
RAM
0h0000
Figure 4-1. Memory mapping
The CPU internal registers are described in the CPU chapter. A short reference of the low power registers and
peripheral registers is given in 4.2.
4.2 Quick reference data memory register map
The data register map is given in the tables below. A more detailed description of the different registers is given in
the detailed description of the different peripherals.
The tables give the following information:
1. The register name and register address
2. The different bits in the register
3. The access mode of the different bits (see Table 4-4-1 for code description)
4. The reset source and reset value of the different bits
The reset source coding is given in Table 4-4-2. To get a full description of the reset sources, please refer to the
reset block chapter.
© Semtech 2005
www.semtech.com
4-2
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