XE8801A – SX8801R
4.2.5
Port C (h0030-h0033)
Name
Address
7
6
5
4
3
2
1
0
RegPCOut
PCOut[7:0]
h0030
rw,00000000,pconf
RegPCIn
PCIn[7:0]
h0031
r,-,-
RegPCDir
PD1Dir[7:0]
h0032
rw,00000000,pconf
Table 4-4-7. Port C registers
4.2.6
Flash programming (h0038-003B)
These four registers are used during flash programming only. Refer to the flash programming algorithm
documentation for more details.
4.2.7
Event handler (h003C-h003F)
Name
Address
RegEvn
h003C
RegEvnEn
h003D
RegEvnPriority
h003E
RegEvnEvn
h003F
7
CntIrqA
rc1,0,sys
r0
6
CntIrqC
rc1,0,sys
r0
5
128Hz
rc1,0,sys
r0
Table 4-4-8. Event handler registers
4
3
PAEvn[1] CntIrqB
rc1,0,sys rc1,0,sys
EvnEn[7:0]
rw,00000000,sys
EvnPriority[7:0]
r,11111111,sys
r0
r0
2
CntIrqD
rc1,0,sys
r0
1
1Hz
rc1,0,sys
EvnHigh
r,0,sys
0
PAEvn[0]
rc1,0,sys
EvnLow
r,0,sys
The origin of the different events is summarised in the table below.
Event
CntIrqA
CntIrqB
CntIrqC
CntIrqD
128Hz
1Hz
PAEvn[1:0]
Event source
Counter/Timer A (counter block)
Counter/Timer B (counter block)
Counter/Timer C (counter block)
Counter/Timer D (counter block)
Low prescaler (clock block)
Low prescaler (clock block)
Port A
Table 4-4-9. Event source description
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