SX8801IRXXMLTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX8801IRXXMLTRT' PDF : 135 Pages View PDF
XE8801A – SX8801R
4.2.8
Interrupt handler (h0040-h0047)
Name
Address
7
RegIrqHig IrqAC
h0040
rc1,0,sys
RegIrqMid UsrtCond1
h0041
rc1,0,sys
RegIrqLow PAIrq[7]
h0042
rc1,0,sys
RegIrqEnHig
h0043
RegIrqEnMid
h0044
RegIrqEnLow
h0045
RegIrqPriority
h0046
RegIrqIrq
h0047
r0
6
128Hz
rc1,0,sys
UrstCond2
rc1,0,sys
PAIrq[6]
rc1,0,sys
r0
5
r0
PAIrq[5]
rc1,0,sys
CntIrqB
rc1,0,sys
r0
Table 4-4-10. Interrupt handler registers
4
3
CntIrqA CntIrqC
rc1,0,sys rc1,0,sys
PAIrq[4]
1Hz
rc1,0,sys rc1,0,sys
CntIrqD PAIrq[3]
rc1,0,sys rc1,0,sys
IrqEnHig[7:0]
rw,0000000,sys
IrqEnMid[7:0]
rw,0000000,sys
IrqEnLow[7:0]
rw,0000000,sys
IrqPriority[7:0]
r,11111111,sys
r0
r0
2
r0
VldIrq
rc1,0,sys
PAIrq[2]
rc1,0,sys
IrqHig
r,0,sys
1
UartIrqTx
rc1,0,sys
PAIrq[1]
rc1,0,sys
0
UartIrqRx
rc1,0,sys
PAIrq[0]
rc1,0,sys
r0
r0
IrqMid
r,0,sys
IrqLow
r,0,sys
The origin of the different interrupts is summarised in the table below.
Event
CntIrqA
CntIrqB
CntIrqC
CntIrqD
128Hz
1Hz
PAIrq[7:0]
UartIrqRx
UartIrqTx
UrstCond1
UsrtCond2
VldIrq
IrqAC
Event source
Counter/Timer A (counter block)
Counter/Timer B (counter block)
Counter/Timer C (counter block)
Counter/Timer D (counter block)
Low prescaler (clock block)
Low prescaler (clock block)
Port A
UART reception
UART transmission
USRT condition 1
USRT condition 2
Voltage level detector
Acquisition chain end of conversion interrupt
Table 4-4-11. Interrupt source description
© Semtech 2005
www.semtech.com
4-6
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