SX8801IRXXMLTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX8801IRXXMLTRT' PDF : 135 Pages View PDF
XE8801A – SX8801R
4.2.2
System, clock configuration and reset configuration (h0010-h001F)
Name
Address
7
RegSysCtrl SleepEn
h0010
rw,0,cold
RegSysReset Sleep
h0011
rw,0,sys
RegSysClock CpuSel
h0012
rw,0,sleep
RegSysMisc
h0013
r0
RegSysWd
h0014
r0
RegSysPre0
h0015
r0
RegSysRcTrim1
h001B
r0
RegSysRcTrim2
h001C
r0
6
EnResPConf
rw,0,cold
ExtClk
r,0,cold
r0
r0
r0
r0
r0
5
EnBusError
rw,0,cold
ResetBusError
rc, 0, cold
EnExtClock
rw,0,cold
r0
r0
r0
Reserved
rw,0,cold
4
EnResWD
rw,0,cold
ResetWD
rc, 0, cold
BiasRC
rw,1,cold
r0
r0
r0
RcFreqRange
rw,0,cold
3
2
1
r0
ResetfromportA
rc, 0, cold
ColdXtal
r,1,sleep
RCOnPA0
rw,0,sleep
r0
r0
ResPad ResPadSleep
rc,0,cold rc,0,cold
ColdRC EnableXtal
r,1,sleep rw,0,sleep
DebFast OutputCkXtal
rw,0,sleep rw,0,sleep
WatchDog[3:0]
s,0000,cold
r0
r0
r0
RcFreqCoarse[3:0]
rw,0000,cold
RcFreqFine[5:0]
rw,10000,cold
0
r0
r0
EnableRC
rw,1,sleep
OutputCpuCk
rw,0,sleep
ResPre
c1r0,0,-
Table 4-4-4. Reset block and clock block registers
4.2.3
Port A (h0020-h0027)
Name
Address
7
6
5
4
3
2
1
0
RegPAIn
PAIn[7:0]
h0020
r
RegPADebounce
PADebounce[7:0]
h0021
rw,00000000,pconf
RegPAEdge
PAEdge[7:0]
h0022
rw,00000000,sys
RegPAPullup
PAPullup[7:0]
h0023
rw,00000000,pconf
RegPARes0
PARes0[7:0]
h0024
rw, 00000000, sys
RegPARes1
PARes1[7:0]
h0025
rw,00000000,sys
Table 4-4-5. Port A registers
4.2.4
Port B (h0028-h002F)
Name
Address
7
6
5
4
3
2
1
0
RegPBOut
PBOut[7:0]
h0028
rw,00000000,pconf
RegPBIn
PBIn[7:0]
h0029
r
RegPBDir
PBDir[7:0]
h002A
rw,00000000,pconf
RegPBOpen
PBOpen[7:0]
h002B
rw,00000000,pconf
RegPBPullup
PBPullup[7:0]
h002C
rw,00000000,pconf
RegPBAna
PBAna[3:0]
h002D
r0
r0
r0
r0
rw,0000,pconf
Table 4-4-6. Port B registers
© Semtech 2005
www.semtech.com
4-4
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