ADSP-2141L View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-2141L' PDF : 39 Pages View PDF
ADSP-2141L
Parameter
Min
Max
Unit
Bus Request/Bus Grant
Timing Requirements:
tBH
BR Hold After CLKOUT High1
tBS
BR Setup Before CLKOUT Low1
0.25tCK + 2
ns
0.25tCK + 17
ns
Switching Characteristics:
tSD
CLKOUT High to xMS, RD, WR Disable
tSDB
xMS, RD, WR Disable to BG Low
tSE
BG High to xMS, RD, WR Enable
tSEC
xMS, RD, WR Enable to CLKOUT High
tSDBH
tSEH
xMS, RD, WR Disable to BGH Low2
BGH High to xMS, RD, WR Enable2
0
0
0.25tCK – 6
0
0
0.25tCK + 10 ns
ns
ns
ns
ns
ns
NOTES
xMS = PMS, DMSL, DMSH, CMS, IOMS, BMS.
1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise, the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
CLKOUT
BR
CLKOUT
PMS, DMSL,
BMS, RD, WR
BG
BGH
t BH
t BS
t SD
t SEC
t SDB
t SE
t SDBH
t SEH
Figure 12. Bus Request/Bus Grant
–22–
REV. 0
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