ADSP-2141L View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-2141L' PDF : 39 Pages View PDF
ADSP-2141L
Parameter
External Memory Read—ADSP-2141L DMA Initiated
Timing Requirements:
tRDD
Read Low to Data Valid
tAA
Address, DMSx Valid to Data Valid
tSUR
Data Valid Before Read Deasserted
tRDH
Data Hold After Read Deasserted
Switching Characteristics:
tA
Clock to Address and DMSx Active
tASR
Address, DMSx Setup Before Read Low
tAH
Address and DMSx Hold After Clock
tRDA
Address, DMSx Hold After Read High
tCRD
Clock High to RD Low
tRP
Read Pulsewidth
tRWR
RD High to Read or Write Low
1. If wait-state(s) added, then referenced to last wait-state clock interval.
2. w = DMA wait states × tCK.
Min
4
1
5
2
2
0.5tCK – 7
8
0.5tCK – 5 + w
0.5tCK – 3
DSP CLOCK
OUT
EXT. ADDR
(A25–0)
EXT. DMSH
EXT. DMSL
EXT. RD
EXT. DATA
(D31–0)
25ns (REF @ 40MHz)
tA
tCRD
tAA
tASR
t RP
tRDA
t RWR
tRDD
tSUR
tRDH
Figure 14. External Memory Read – ADSP-2141L DMA Initiated
Max
Unit
0.5tCK – 8 + w ns
0.5tCK – 3 + w ns
ns
ns
9
ns
ns
ns
ns
12
ns
ns
ns
t AH
–24–
REV. 0
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