ADSP-2141L View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-2141L' PDF : 39 Pages View PDF
ADSP-2141L
Parameter
Min
Max
IDMA Write, Long Write Cycle (IDMA Mode, Multiplex Bus)
Timing Requirements:
tIKW
tIKSU
tIKH
MPLX9 Low Before Start of Write1
MPLX_BUS Data Setup Before MPLX9 Low2, 3, 4
MPLX_BUS Data Hold After MPLX9 Low2, 3, 4
0
0.5tCK + 10
2
Switching Characteristics:
tIKLW
Start of Write to MPLX9 Low4
tIKHW
Start of Write to MPLX9 High
1.5tCK
15
NOTES
1Start of Write = MPLX7 Low and MPLX6 Low.
2If Write Pulse ends before MPLX9 Low, use specifications tIDSU, tIDH.
3If Write Pulse ends after MPLX9 Low, use specifications tIKSU, tIKH.
4This is the earliest time for MPLX9 Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.
Unit
ns
ns
ns
ns
ns
/ MPLX9 IACK
/ MPLX7 IS
t IKW
t IKHW
t IKLW
/ MPLX6 IWR
/ MPLX_BUS IAD15–0
t IKSU
DATA
t IKH
Figure 20. IDMA Write, Long Write Cycle (IDMA Mode, Multiplex Bus)
–30–
REV. 0
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