ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
ADSP-21469/ADSP-21469W
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left justified, I2S, or right justified with word widths of 16-, 18-,
20-, or 24-bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 29 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
Preliminary Technical Data
mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
DAI_P20-1
LRCLK
DAI_P20-1
SCLK
DAI_P20-1
LSB
SDATA
LEFT CHANNEL
MSB MS B-1 MSB-2
LSB+2 LSB+1 LSB
Figure 29. Right-Justified Mode
Figure 30 shows the default I2S-justified mode. LRCLK is low
for the left channel and HI for the right channel. Data is valid on
the rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.
RIGHT CHANNEL
MSB MSB-1 MSB-2
LSB+2 LSB+1 LSB
DAI_P20-1
LRCLK
LEFT CHANNEL
RIGHT CHANNEL
DAI_P20-1
SCLK
DAI_P20-1
SDATA
MSB MSB-1 MS B-2
LSB+2 LSB+1 LSB
MSB MS B-1 MSB-2
LSB+2 LSB+1 LSB
MSB
Figure 30. I2S-Justified Mode
Figure 31 shows the left-justified mode. LRCLK is high for the
left channel and LO for the right channel. Data is valid on the
rising edge of SCLK. The MSB is left-justified to an LRCLK
transition with no MSB delay.
DAI_P20-1
LRCLK
DAI_P20-1
SCLK
DAI_P20-1
SDATA
MSB MSB-1 MSB-2
LEFT CHANNEL
RIGHT CHANNEL
LS B+2 LSB+1 LSB
MSB MSB-1 MSB-2
Figure 31. Left-Justified Mode
LSB+2 LSB +1 LSB
MSB MSB+1
Rev. PrB | Page 42 of 56 | November 2008
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