ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
ADSP-21469/ADSP-21469W
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the TBD × FS clock.
Table 41. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter
Min
Switching Characteristics
tDFSI
LRCLK Delay After SCLK
TBD
tHOFSI
LRCLK Hold After SCLK
TBD
tDDTI
Transmit Data Delay After SCLK
TBD
tHDTI
Transmit Data Hold After SCLK
TBD
tSCLKIW1
Transmit SCLK Width
TBD
1 SCLK frequency is TBD x FS where FS = the frequency of LRCLK.
Preliminary Technical Data
Max
Unit
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
DRIVE EDGE
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
tHOFSI
tHDTI
tDFSI
tSCLKIW
tDDTI
SAMPLE EDGE
Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing
Rev. PrB | Page 44 of 56 | November 2008
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