ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
Preliminary Technical Data
ADSP-21469/ADSP-21469W
JTAG Test Access Port and Emulation
Table 46. JTAG Test Access Port and Emulation
Parameter
Min
Timing Requirements
tTCK
TCK Period
TBD
tSTAP
TDI, TMS Setup Before TCK High
TBD
tHTAP
TDI, TMS Hold After TCK High
TBD
tSSYS1
System Inputs Setup Before TCK High
TBD
tHSYS1
System Inputs Hold After TCK High
TBD
tTRSTW
TRST Pulse Width
TBD
Switching Characteristics
TBD
tDTDO
TDO Delay from TCK Low
TBD
tDSYS2
System Outputs Delay After TCK Low
TBD
1 System Inputs = AD15–0, CLKCFG1–0, RESET, BOOTCFG1–0, DAI_Px, and FLAG3–0.
2 System Outputs = DAI_Px, AD15–0, AMI_RD, AMI_WR, FLAG3–0, CLKOUT, EMU, and ALE.
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tTCK
tSTAP
tDTDO
tSSYS
tDSYS
tHTAP
tHSYS
Figure 38. IEEE 1149.1 JTAG Test Access Port
Rev. PrB | Page 49 of 56 | November 2008
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