ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
ADSP-21469/ADSP-21469W
OUTPUT DRIVE CURRENTS
Figure 39 shows typical I-V characteristics for the output driv-
ers of the ADSP-21469. The curves represent the current drive
capability of the output drivers as a function of output voltage.
12
10
8
TBD
6
4
2
0
0
50
100
150
200
250
Figure 39. ADSP-21469 Typical Drive at Junction Temperature
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 15 on Page 23 through Table 46 on Page 49. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 40.
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 41. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
VLOAD
50:
70:
50:
4pF
2pF
400:
TESTER PIN ELECTRONICS
45:
0.5pF
T1
DUT
OUTPUT
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 40. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Preliminary Technical Data
INPUT
OR 1.5V
OUTPUT
1.5V
Figure 41. Voltage Reference Levels for AC Measurements
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 40). Figure 44 shows graphically
how output delays and holds vary with load capacitance. The
graphs of Figure 42, Figure 43, and Figure 44 may not be linear
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) vs. Load Capacitance.
12
10
8
TBD
6
4
2
0
0
50
100
150
200
250
Figure 42. Typical Output Rise/Fall Time (20% to 80%,
VDD_EXT = Max)
12
10
8
TBD
6
4
2
0
0
50
100
150
200
250
Figure 43. Typical Output Rise/Fall Time (20% to 80%,
VDD_EXT = Min)
Rev. PrB | Page 50 of 56 | November 2008
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